The following document was submitted by Dennis Armstrong.
Thanks to Frank Lockwood for putting me in touch with Dennis.
Atari TT RAM cards
Atari produced two TT memory boards: the CA400312-xxx which uses four 1 MB 30-Pin SIMMs (4MB) and the CA401058-xxx which is capable of using either four 1 MB 30 Pin SIMMS (4 MB) or four 4 MB SIMMS (16 MB).
Atari 4 MB TT RAM board
The Atari TT fastram board CA400312-xxx has three jumpers marked W1, W2 and W3. These are used to select starting address and mode:
Address Mode jumper W3 NON-BURST 1 - 2 BURST 2 - 3
The starting address is set with the following jumpers:
Starting Address jumper W1 jumper W2 $0100 0000 2 - 3 2 - 3 $0140 0000 1 - 2 2 - 3 $0180 0000 2 - 3 1 - 2 $01C0 0000 1 - 2 1 - 2 Location:
pin 32 pin 12 _________________ --------- pin 33 | | pin 11 pin 1| | | | | | | | | | | TTFMCU | | RP101 | | | --------- | | --------- pin 53 | | pin 75 | RP102 | ---------------- | | pin 54 pin 74 | | | | W3 | | W2 _________ W1 | | | | | | | | | | | | SIMMs --> | | | | | | | | | | | |It is possible to upgrade this board to use 4 MB SIMMS for 16MB of TT RAM. The instructions for performing the upgrade are here.
Atari 4/16MB TT RAM board
The Atari TTFAST ram board (CA401058-xxx) uses 30 pin SIMMs. The SIMMs may be 1M x 8 or 4M x 8 (9 bit SIMMs may also be used). All 4 SIMM slots should have the same type (ie. 1M or 4M). 1M SIMMs give a total of 4Mb of fast ram, 4M SIMMs give a total of 16Mb.
The jumpers required are as follows:
SIMM type jumper W101 jumper W102 jumper W106 1M x 8 2 - 3 2 - 3 2 - 3 4M x 8 1 - 2 1 - 2 1 - 2
Starting RAM address jumper W103 jumper W104 $0100 0000 2 - 3 2 - 3
Address Mode jumper W105 NON-BURST 1 - 2 BURST 2 - 3 (default) Location:
| mmu chip | | | ________________ W105 W106 W104 W103 W102 W101 | | | | | | | | SIMM slots -> | | | | | | | | | | | |It is possible that during manufacture there was a shortage of SIMM holders and SIPPs were used. The pinout is identical to SIMMs but pins were soldered to the connectors. If this is the case then you will have to purchase some SIMM holders if you require to change the configuration.
BURST and NON-BURST modes
The following is a usenet post from Howard Chu, explaining the differences between BURST and NON-BURST modes:Joe Mirando (jmirando@streport.com) wrote:
Can anyone enlighten me as to the purpose of TT RAM "burstmode"? I'm in the process of increasing TT RAM from 4 to 16 meg and saw the burst/no burst jumper on the RAM board, but have no idea what the difference is.
Burst mode requires special SIMMs to operate. They used to be called nybble-mode DRAMs, but (practically) no one in the memory industry today sells them or has even heard of them. I'm told that EDO memory now common on PCs uses the same concept, but I don't know if they are directly compatible.
The fully gory discussion requires an explanation of CPU memory accesses, bus timing, and other such info, but can be distilled into this much:
Ordinarily, when a CPU wanted to get something from memory, it would first have to assert an address for some number of bus cycles, and then the word of data would become available some number of cycles later. For every word being accessed, an address had to be asserted first. In burst mode, the CPU asserts an address and a special "burst" signal, and the memory system returns the word at the requested address first, and then on the following three bus cycles it returns the following three words, in rapid succession. This saves the setup time that normally goes with asserting the address, etc.
On a 68000, a byte or word memory access always required 4 cycles. On 68020 this could usually be cut down to 3 cycles, and longwords could also be accessed in this amount of time. On 68030 in burst mode, you can get the first longword in 4 cycles, and then 3 more longwords in 3 more cycles, so instead of 12-16 cycles, you're only using 7.
There are several restrictions, of course - you must start from a 4-word aligned address (i.e., memory addresses that are integral multiples of 4), you must be doing 32-bit (longword) accesses, and the memory system must support synchronous bus cycles. Also the 68030 only performs burst accesses on read operations, specifically for filling its instruction cache. On 68040, a MOVE16 instruction was added that allowed reads & writes of 16 byte chunks of data (as opposed to just instructions) in burst mode.
Btw, in case it wasn't obvious before, the memory is called "nybble-mode" because each chip returns 4 bits of data on a burst request, instead of just 1 bit. And on 8 or 9 chip SIMMs, there are 8 chips because each chip stores a single bit of a particular data byte. (The 9th chip stores parity bits when it's being used.)
As you can see, the 68030 burst implementation has very limited impact on overall system performance. For code that does not loop, or that does not fit inside the instruction cache, instruction fetches can occur almost 180% faster than otherwise. Data fetches aren't improved though, and code that is already in the instruction cache is already running as fast as possible.
-- Howard Chu Principal Member of Technical Staff hyc@highlandsun.com PLATINUM technology, Los Angeles Lab