Voice Interface:	Pin Layout of the used chips
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SP0256-AL2 Pin layout

Pin		Name			Function
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1		Vss			Ground
2		RESET			Reset
3		ROM DISABLE		Disable external ROM (unused here)
4		C1			
5		C2			Output control lines for speach ROM
6		C3
7		VDD			Power supply (except interface logic)
8		SBY			Standby (logic 1 if inactive)
9		LRQ			Load request	
					(logic 0 if input buffer empty)
10		A8			(unused)
11		A7			(unused)
12		SER OUT			Output to external ROM (unused)
13		A6			Phoneme address bit 5
14		A5			Phoneme address bit 4
15		A4			Phoneme address bit 3
16		A3			Phoneme address bit 2
17		A2			Phoneme address bit 1
18		A1			Phoneme address bit 0
19		SE			Strobe enable (non-automatic load)
20		ALD			Address Load (Strobe)
21		SER IN			Input from external ROM (unused)
22		TEST			Must be grounded
23		VD1			Power supply for the interface logic
24		DG OUT			Digital ouput (sound output)
25		SBY RESET		Standby Reset 
					(logic 0 resets the interface logic)
26		ROM CLOCK		Clock output for the speach rom
27		OSC1			XTAL IN.
28		OSC2			XTAL OUT for the 3.12 MHz crystal



6522 VIA Pin Layout A 
(Make sure you get the 2 MHz version. The 1MHz version is too slow.)
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1		Vss			Ground
2		PA0			Port A bit 0
3		PA1
4		PA2
5		PA3
6		PA4
7		PA5
8		PA6
9		PA7			Port A bit 7
10		PB0			Port B bit 0
11		PB1
12		PB2
13		PB3
14		PB4
15		PB5
16		PB6
17		PB7			Port B bit 7
18		CB1			Control line 1 port B
19		CB2			Control line 2 port B
20		Vcc			Supply voltage
21		IRQ			Interrupt output
22		R/W			Read/Write input
23		CS2			Chip select input
24		CS1			Chip select input
25		Phi2			Clock input
26		D7			Data bit 7
27		D6
28		D5
29		D4
30		D3
31		D2
32		D1
33		D0			Data bit 0
34		RES			Reset input
35		RS3			Address line 3
36		RS2			Address line 2
37		RS1			Address line 1
38		RS0			Address line 0
39		CA2			Control line 2 port A
40		CA1			Control line 1 port A


LM 324	Quad OP AMP
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1		Out  A
2		In - A
3		In + A
4		positive supply voltage
5		In + B
6		In - B
7		Out  B
8		Out  C
9		In - C
10		In + C
11		negative supply voltage
12		In + D
13		In - D
14		Out  D


LM 741	OP AMP
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1		Offset
2		In -
3		In +
4		negative supply voltage
5		Offset
6		Output
7		positive supply voltage
8		unused


Atari Parallel Port Pin Layout (System bus)
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1		GND			Ground
2		EXTSEL			External RAM Select
3		A0			Address line 0
4		A1
5		A2
6		A3
7		A4
8		A5
9		A6			Address line 6
10		GND			Ground
11		A7			Address line 7
12		A8
13		A9
14		A10
15		A11
16		A12
17		A13
18		A14			Adress line 14
19		GND			Ground
20		A15			Adress line 15
21		D0			Data line 0
22		D1
23		D2
24		D3
25		D4
26		D5
27		D6
28		D7			Data line 7
29		GND			Ground
30		GND			Ground
31		B02			Phase 2 clock output
32		GND			Ground
33		N.C.			Reserved
34		RST			Reset output
35		IRQ			IRQ input
36		RDY			Ready input
37		N.C.			Reserved
38		EXTENB			ExtenB output
39		N.C.			Reserved
40		REFRESH			Refresh output
41		CAS			Column select for RAM, output
42		GND			Ground
43		MPD	(*)		MathPack Disable input
44		RAS			Row select for RAM, output
45		GND			Ground
46		LR/W			Buffered read/write signal
47		N.C.	(*)		Reserved
48		N.C.	(*)		Reserved
49		AUDIO			Audio IN
50		GND			Ground

Notes:

-	(*)	These lines are affected by the hardware hack required
		by the interface.

		MPD (43) is connected with pin 16 of the internal PIA 6520A,
		U23

		Pin 47 (N.C.) is connected with the positive power supply.
		Pin 48 (N.C.) is connected to pin 9 of the address decoder
		74LS138, U2 and provides an address selection signal for
		the range $d600 to $d6ff.

- Additional Note: Pin 1 of the atari port is in the upper right edge 
of the port, pin two is below pin one, the numbers grow from the RIGHT 
to the LEFT if you look on the connector from the rear side of the computer.