53760



     number for the desired clock frequency. You then set the volume
     to zero in the AUDC register associated with the AUDF register
     you plan to use as a timer. You load the AUDF register itself with
     the number of clock intervals you wish to count. Then you load
     your interrupt routine into memory, and POKE the address into the
     appropriate timer vector between locations 528 and 533 ($210 and
     $215). You must set the proper bit(s) in IRQEN and its shadow
     register POKMSK at location 16 ($10) to enable the interrupt.
     Finally, you load STIMER with any value to load and start the
     timer(s). The OS will force a jump to the timer vector and then to
     your routine when the AUDF register counts down to zero. Timer
     processing can be preempted by ANTIC's DMA, a DLI, or the
     VBLANK process.

     POT values are for the paddles, ranging from zero to 240,
     increasing as the paddle knob is turned counterclockwise, but
     values less than 40 and greater than 200 represent an area on
     either edge of the screen that may not be visible on all TV sets or
     monitors.

53760          D200           AUDF1
     (W) Audio channel one frequency. This is actually a number (N)
     used in a "divide by N circuit"; for every N pulses coming in (as set
     by the POKEY clock), one pulse goes out. As N gets larger, output
     pulses will decrease, and thus the sound produced will be a lower
     note. N can be in the range from one to 256; POKEY adds one to
     the value in the AUDF register. See BYTE, April 1982, for a
     program to create chords instead of single tones.

                              POT0
     (R) Pot (paddle) 0 (624); pot is short for potentiometer. Turning the
     paddle knob clockwise results in decreasing pot values. For
     machine language use: these pot values are valid only 228 scan
     lines after the POTGO command or after ALLPOT changes (see
     53768; $D208 and 53771; $D20B). POT registers continually count
     down to zero, decrementing every scan line. They are reset to 228
     when they reach zero or by the values read from the shadow
     registers. This makes them useful as system timers. See
     COMPUTE!, February 1982, for an example of this use.

     The POTGO sequence (see 53771; $D20B) resets the POT
     registers to zero, then reads them 228 scan lines later. For the fast
     pot scan, BIT 2 of SKCTL at 53775 ($D20F) must be set.

53761          D201           AUDC1
     (W) Audio channel one control. Each AUDF register has an
     associated control register which sets volume and distortion levels.
     The bit assignment is: