; ---------------------------
; Infrared gateway code (IRG)
; Simple version to be used
; with IRGSCAN.BAS
; (c) 1993 David Deaven
; ---------------------------
	include <atarios.h>

bufadd = 203 ; and 204
bufsiz = 205
bytbuf = 206
sample = 207

	org $600

	PROC	; BASIC "USR" entry
USR	LDA #0
	SEI		; stop IRQ...
	STA NMIEN	; ...and NMI
	STA DMACTL	; prevent DMA
	STA FR0+1	; zero return

	LDA #%0011_1001	; set up PIA
	STA PACTL	; bit A0 output
	LDA #%0000_0001
	STA PORTA
	LDA #%0011_1101
	STA PACTL

	PLA		; get # args
	TAY
	CPY #3		; need 4 args
	BMI :badarg
	
	PLA
	STA bufadd+1
	PLA
	STA bufadd
	DEY

	PLA
	PLA
	STA bufsiz
	DEY

	PLA
	PLA
	STA sample
	DEY
	BEQ Send ; 3 arg --> SEND

	PLA
	STA totime
	PLA
	STA qtime
	DEY
	BEQ Receive ; 4 arg --> RECEIVE

:badarg	TYA		; pop all args
	BEQ Exit 	; and return
:nexta	PLA
	PLA
	DEY
	BNE :nexta
	BEQ Exit
	EPROC

	PROC
;
; Fill the buffer with data.
;
Receive	LDY #0		; detect gap
	LDA #1		; IR is LSB
:wait	JSR Delay
	BIT TRIG0
	BEQ Receive
	INY
	CPY qtime
	BNE :wait

	LDY totime
:mark0	LDX qtime
:mark	BIT TRIG0
	BEQ :start
	JSR Delay ; wait -- first pulse
	DEX
	BNE :mark
	DEY
	BNE :mark0
	LDY #1
	JMP Exit ; timeout

:start	LDY #0
	LDX #8
:loop	LDA TRIG0	; 4
	ROR A		; 2
	ROL bytbuf	; 5
	JSR Delay	; 6 + delay
	DEX		; 2
	BNE :no		; 3
	LDA bytbuf	; 3
	EOR #$FF	; 2
	STA (bufadd),Y	; 6
	LDX #8		; 2
	INY		; 2
	CPY bufsiz	; 4
	BNE :loop	; 3
	LDY #0
	BEQ Exit
:no	JSR adjust	; 6+10 cycles
	NOP		; 2
	JMP :loop	; 3
	EPROC

;
; Exit -- restart DMA, interrupts
;
Exit	STY FR0		; return code
	LDA SDMCTL	; enable DMA
	STA DMACTL
	LDA #$40	; enable NMI
	STA NMIEN
	CLI		; enable IRQ
	RTS

;
; Send the buffer out
;
	PROC
Send	LDY #$FF
	LDX #8
:loop	INY		; 2 cycles
	LDA (bufadd),Y	; 5
	STA bytbuf	; 3
:sloop	ROL bytbuf	; 6
	LDA #0		; 2
	ROL A		; 2
	STA PORTA	; 4
	JSR Delay	; 6 + delay
	DEX		; 2
	BNE :no		; 3
	LDX #8		; 2
	CPY bufsiz	; 4
	BNE :loop	; 3
	LDY #0
	BEQ Exit
:no	JSR adjust	; 6+10 cycles
	JMP :sloop	; 3
	EPROC

; waste 10 cycles
adjust	NOP		; 2 cycles
	NOP		; 2 cycles
	RTS		; 6
	
	PROC
;
; Wait a delay time, preserve A, X, Y
; time = (20+5*sample) clock periods
; 
Delay	PHA		; 3 cycles
	TXA		; 2
	LDX sample	; 3
:loop	DEX		; 2
	BNE :loop	; 3
	TAX		; 2
	PLA		; 4
	RTS		; 6
	EPROC

qtime	DB 0
totime	DB 0

	assert * < $700
	END