Hardware Description

The MIO has 3 basic addressing areas: 1) ACIA at $D1C0-$D1DF, 2) MIO Latches at $D1E0-$D1FF, and 3) 256 bytes of RAM at $D600-$D6FF. Note that the ACIA and MIO latches are not fully decoded; both contain 4 read/write registers, but each register has 7 shadows. Tables 5-1 through 5-3 briefly describes the MIO registers.

ACIA Operation

For more information on the ACIA operation, refer to a 6551A or 65C51 data manual (this part is manufactured by Rockwell, GTE, NCR, and RCA). The only irregularity of usage is that the lines DSR, CTS, and DCD are tied to ground. This is due to the fact that the ACIA will not receive data if either of these lines are false. To read the actual state of these lines, you must read location $D1E3 (bits 2,1,0). This will return the true lines sense (DCD true is indicated by a high on bit 1 of $D1E3).

SASI/SCSI Interface

The data input/output ($D1E1) and input control lines ($D1E2) reflect the true voltage levels on the ports. Thus, the input control lines are normally all ones (port voltages are +5) which represents a logic false on the bus. For more information on SASI/SCSI bus protocol, refer to the Adaptec ACB-4000 Series User's Manual, the XEBEC S1410A disk controller document, the Seagate ST225N manual, or any other device manual employing these protocols.

The ACK-/REQ- handshake cycle is performed by the MIO hardware. Whenever the data ($D1E1) is read or written, ACK- is set true. It is cleared by a high level on the REQ- input signal.

The RST- is set true when $D1E0 is read or when the RESET key pressed on the computer (or during powerup). It is cleared by reading location $D1E2.

The I/O- controls whether the 8-bit printer/SASI registers are input or output. When I/O- is high (input to SASI controller), the data is output on the printer and SASI port. If I/O- is low, then the output latches are disabled (it will latch new data, but the output is tri-stated).

Printer Interface

The printer data ($D1E1) and BUSY signals are high true logic. The a high (1) on BUSY (bit 6 of $D1E2) indicates the printer is busy. A low (0) on FAULT- (bit 4 of $D1E2) reflects an error condition in the printer (printer off?).

Table 5-1. MIO Register Selection

Note
* The transmitter is disabled immediately. The receiver is disabled but will first complete receiving the byte in process.

Addressing the RAM

The MIO can access up to 1 Megabyte of RAM which takes 20 bits to address. Address bits A19-A16 are set from writing to the latch at $D1E2, bits A15-A8 are set from writing to the latch at $D1E0, and bits A7-A0 are CPU address lines A7-A0 when reading/writing $D6xx. Thus there are up to 4096 "pages" of memory that may appear at the $D6xx window.

In order to access the memory, it must first be enabled by setting $D1E2 bit 5 to "1" (this also turns on the MIO's red LED). It is generally a good idea to leave the RAM disabled while not using it in case of a system crash (which could inadvertently write in the $D6xx window).

When power is removed from the computer (for whatever reason), the MIO will continue refreshing its dynamic RAM. This is accomplished by its ability to maintain a 02 clock after the computers clock has stopped. VC1 adjusts the MIO's 02 clock frequency. Adjustment requires special equipment and should not be attempted.

Checking IRQ Status

The MIO has two sources of interrupts; one is the ACIA and the other is the parallel printer port. The printer port may interrupt the computer only if bit 7 of $D1E2 is set ('1') and the printer BUSY is false ('0'). Bit 4 of $D1E3 is the general IRQ flag from the MIO (a 1 indicates that IRQ- is true). If bit 3 is also set, then the IRQ- is caused by the printer. If not, then it must be the ACIA (in which case $D1C1 bit 7 should be set).

Note that the parallel device IRQ mask (PDIMSK at $249) is set to $10 by the MIO RAM. This is because, there is only one interrupt handler (which supports all possible MIO interrupts) in the ROM. In fact, the system would crash if the OS tried to enter any of the other ROM banks to service the IRQ.

Accessing the ROM

The ROM on the MIO contains all the software necessary to access the hard disk, the RAM, the ACIA (as an R: or P:), and the parallel printer port. It also contains the configuration which is downloaded into the computer RAM when SELECT+RESET are pressed.

The ROM is accessed as 4-2K banks. (An additional 8K is reserved for the 80 column adapter.) Bits 5-2 (of $D1E3) select which bank will be active (if any) at the $D800-$DFFF region. Only 1 bit may be set and its position selects which bank of ROM is active. If all bits are zero, then no banks are active and the Floating Point Math package in the OS ROM is enabled.

According to Atari spec, 1 device is to occupy one bank of ROM and that device has a specific address range legal to it at $D1xx. Since the MIO is an all inclusive device, however, it deviates from this spec. Instead, it tries to cram as much code as possible into a small space. This meant juggling the banks around to get along with the computer and to allow for expansion of an 80 column adapter. This is why there is only one interrupt handler, yet several input bits are returned in what is considered to be strictly an interrupt sense register (at $D1FF).

Software Description

In order for the MIO to perform its multitude of tasks, one full page of memory has been allocated for general operating variables and configuration parameters. Two other pages have been reserved for "R:" handler input and output buffers, and the rest of memory (up to 4093 pages) can be used as RAM drives and a printer buffer through the MIO ROM. Table 5-4 describes the configuration parameters (those which are read from the hard disk (ID=0, LUN=0) when memory is invalid). This table occupies the first 192 bytes of memory page 0. The remaining 64 bytes are operating variables and are listed in table 5-5. Memory pages 1 and 2 are reserved for the "R:" handler input/output buffers.

Table 5-4. MIO Configuration Parameters

Table 5-5. MIO Operating Variables