Heavily modified from the SmartIDE schematic.  This is still an internal design that plugs into the CPU socket for 
most of the signals needed.  No PAL/GAL logic is used.  The .SCH file was created using Eagle v3.55r3.  
No code has yet been developed as I have not yet built this circuit.  Where the previous design used 0xD100-0xD13F 
for the upper 8 data bits, this design should have that area located at 0xD140-0xD147.  The entire board acts as one 
PBI device.  The LCD interface should be full read/write, as with the battery backed SRAM for the PBI code and the SRAM 
for the 0xD600-0xD7FF.  The design allows for 16 banks of 2k bytes @ 0xD800-0xDFFF and 16 banks of 
512 bytes @ 0xD600-0xD7FF.