Atari "Sally" (6502) Instruction Set

Op-Code Table (listed by instruction):

	IMPLIED			ACCUM.			IMMEDIATE			Z PAGE			Z PAGE, X			Z PAGE, Y			(IND, X)			(IND), Y			ABS, X			ABS, Y			ABSOLUTE			INDIRECT			RELATIVE
MNEMONIC	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ	OP	B	µ
ADC							69	2	2	65	2	3	75	2	4				61	2	6	71	2	5	7D	3	4	79	3	4	6D	3	4
ANC *							0B 2B	2	2
AND							29	2	2	25	2	3	35	2	4				21	2	6	31	2	5	3D	3	4	39	3	4	2D	3	4
ARR *							6B	2	2
ASL				0A	1	2				06	2	5	16	2	6										1E	3	7				0E	3	6
ASR							4B	2	2
ASX *							CB	2	2
AX7 *																						93	2	5				9F	3	5
AXE *							8B	2	2
BCC																																					90	2	†
BCS																																					B0	2	†
BEQ																																					F0	2	†
BIT										24	2	3																			2C	3	4
BMI																																					30	2	†
BNE																																					D0	2	†
BPL																																					10	2	†
BRK	00	1	7
BVC																																					50	2	†
BVS																																					70	2	†
CLC	18	1	2
CLD	D8	1	2
CLI	58	1	2
CLV	B8	1	2
CMP							C9	2	2	C5	2	3	D5	2	4				C1	2	6	D1	2	5	DD	3	4	D9	3	4	CD	3	4
CPX							E0	2	2	E4	2	3																			EC	3	4
CPY							C0	2	2	C4	2	3																			CC	3	4
DCP *										C7	2	5	D7	2	6				C3	2	8	D3	2	8	DF	3	7	DB	3	7	CF	3	6
DEC										C6	2	5	D6	2	6										DE	3	7				CE	3	6
DEX	CA	1	2
DEY	88	1	2
EOR							49	2	2	45	2	3	55	2	4				41	2	6	51	2	5	5D	3	4	59	3	4	4D	3	4
INC										E6	2	5	F6	2	6										FE	3	7				EE	3	6
INX	E8	1	2
INY	C8	1	2
ISB *										E7	2	5	F7	2	6				E3	2	8	F3	2	8	FF	3	7	FB	3	7	EF	3	6
JAM *	¤	1	00
JMP																															4C	3	3	6C	3	5
JSR																															20	3	6
LAS *																												BB	3	4
LAX *										A7	2	3				B7	2	4	A3	2	6	B3	2	5				BF	3	4	AF	3	4
LDA							A9	2	2	A5	2	3	B5	2	4				A1	2	6	B1	2	5	BD	3	4	B9	3	4	AD	3	4
LDX							A2	2	2	A6	2	3				B6	2	4										BE	3	4	AE	3	4
LDY							A0	2	2	A4	2	3	B4	2	4										BC	3	4				AC	3	4
LSR				4A	1	2				46	2	5	56	2	6										5E	3	7				4E	3	6
NOP	EA	1	2				§	2	2	§	2	3	§	2	4										§	3	4				§	3	4
ORA							09	2	2	05	2	3	15	2	4				01	2	6	11	2	5	1D	3	4	19	3	4	0D	3	4
PHA	48	1	3
PHP	08	1	3
PLA	68	1	4
PLP	28	1	4
RLA *										27	2	5	37	2	6				23	2	8	33	2	8	3F	3	7	3B	3	7	2F	3	6
ROL				2A	1	2				26	2	5	36	2	6										3E	3	7				2E	3	6
ROR				6A	1	2				66	2	5	76	2	6										7E	3	7				6E	3	6
RRA *										67	2	5	77	2	6				63	2	8	73	2	8	7F	3	7	7B	3	7	6F	3	6
RTI	40	1	6
RTS	60	1	6
SAX *										87	2	3				97	2	4	83	2	6										8F	3	4
SBC SBC *							E9 EB	2 2	2 2	E5	2	3	F5	2	4				E1	2	6	F1	2	5	FD	3	4	F9	3	4	ED	3	4
SEC	38	1	2
SED	F8	1	2
SEI	78	1	2
SRA *										07	2	5	17	2	6				03	2	8	13	2	8	1F	3	7	1B	3	7	0F	3	6
SLO *										47	2	5	57	2	6				43	2	8	53	2	8	5F	3	7	5B	3	7	4F	3	6
STA										85	2	3	95	2	4				81	2	6	91	2	6	9D	3	5	99	3	5	8D	3	4
STX										86	2	3				96	2	4													8E	3	4
STY										84	2	3	94	2	4																8C	3	4
SX7 *																												9E	3	5
SY7 *																									9C	3	5
TAX	AA	1	2
TAY	A8	1	2
TSX	BA	1	2
TXA	8A	1	2
TXS	9A	1	2
TYA	98	1	2
XEA *							AB	2	2
XS7^*																												9B	3	5

Legend:

OP: Op-code

B: Number of bytes required

µ: Number of cycles used to execute the instruction

Addressing modes:

IMPLIED: The operands are indicated in the mnemonic.

ACCUM. (A): The operand is the accumulator.

IMMEDIATE (IMM): The operand is the byte following the opcode.

Z PAGE: The byte following the opcode is the address on page 0 of the operand.

Z PAGE,X: The byte following the opcode is added to register X to give the address on page 0 of the operand.

Z PAGE,Y: The byte following the opcode is added to register Y to give the address on page 0 of the operand.

(IND,X): The byte following the opcode is added to register X to give the address on page 0 which contains the address of the operand.

(IND),Y: The byte following the opcode is an address on page 0. This word at this address is added to register Y (as an unsigned word) to give the address of the operand.

ABS,X: The word following the opcode is added to register X (as an unsigned word) to give the address of the operand.

ABS,Y: The word following the opcode is added to register Y (as an unsigned word) to give the address of the operand.

ABSOLUTE (ABS): The word following the opcode is the address of the operand.

INDIRECT: The word following the opcode is the address of a word which is the address of the operand.

RELATIVE: The byte following the opcode is added (as a signed word) to the Program Counter to give the address of the operand.

Notes:

* Undocumented instruction. The behavior of these opcodes was observed on an Atari 800. It may vary with other 6502-based CPU's.

† Branch instructions take 2 cycles if branch is not taken, 3 cycles if branch is taken within the same page, 4 cycles if branch is taken to another page.

¤ There are multiple opcodes for the JAM instruction: 02, 12, 32, 42, 52, 62, 72, 92, B2, D2, and F2.

§ There are multiple opcodes for the NOP instruction; EA is the official one. For implied mode: 1A, 3A, 5A, 7A, DA, EA, and FA. For immediate mode: 80, 82, 89, C2, and E2. For Zero Page mode: 04, 44, and 64. For Zero Page, X mode: 14, 34, 54, 74, D4, and F4. For Absolute, X mode: 1C, 3C, 5C, 7C, DC, and FC. For Absolute mode: 0C.

Atari "Sally" (6502) Instruction Set

Op-Code Table (listed by instruction):

Legend:

Addressing modes:

Notes:

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