--*************************************************************************/
--                                                                        */
--C025953PAL16L8 - replacement for C025953 Atari 130XE chip using         */
--		    the placement option on the 130XE PCB:                */
--	    PAL/GAL16L8/16V8 and a 74LS95 as U35                          */
--      								  */
--	    The circuit diagramm of the 130XE is wrong with               */
--		    regard to the U35 pinout. Here is the correct         */
--	    U35 pinout:						          */
--								          */
--	    pin 1:	HALT from U7 pin 9			          */
--	    pin 2-7: 	GND					          */
--	    pin 8: 	GND					          */
--                 pin 9:	Bphi2 (buffered phi2)                     */
--	    pin 10-12   NC					          */
--	    pin 13:	mhalt (to U34 pin 11)			          */
--	    pin 14:	VCC (+5V)				          */
--	 						   		  */
--HALT is being latched using a 74LS95 shift register (U35) with the 	  */
--falling edge of phi2. That provides a delayed variant of the ANTIC      */
--HALT signal (mhalt) which gets active (low) in the particular bus cycle */
--that  								  */
--ANTIC wants to take over. This is necessary because the original HALT   */
--from ANTIC is set active (low) the bus cycle BEFORE the particular 	  */
--bus cycle that ANTIC wants to take over (see logic analyser screenshots */
--on http://home.cablesurf.de/christopher.lang/atari-8-bit/). 		  */
--									  */
--In other words:                                                         */
--mhalt is the latched halt signal. It is being latched with the falling  */
--edge of phi2. That brings mhalt exactly into the bus cycle that ANTIC   */
--just asked for and now can be used to distiguish between CPU bus cycles */
--and ANTIC bus cycles.						          */
--								          */
--cas is being let gone to either casb or casm only when phi 2 is high    */
--(the 2nd half of the 6502 bus cycle). This prevents from junk on the    */
--casm and casb lines because the original cas signal is longer than the  */
--actual 6502 bus cycle and crosses over into the next 6502 bus cycle     */
--catching all kinds of junk. This shortens the cas signals a bit but     */
--still works properly.					  	          */
--								          */
--The original C025953 lets the full length cas signal pass, so it 	  */ 
--actually latches the cas pass through with the rising edge of phi2	  */
--in order to avoid junk on the cas lines.				  */
--									  */
--This design adds a mode pin: pin 12 of the GAL/PAL. 			  */
--								          */
--mode pin set to 0 chooses 130XE compatibility mode, 			  */
--mode pin set to 1 chooses 800XL mode					  */
--                                                                        */
--many thanks to http://www.s-direktnet.de/homepages/k_nadj/xebanks.html  */
--thanks as well to http://cat.asw.cz/~kubecj/achemmu.htm                 */
--								          */ 
--IMPORTANT NOTE: for this design to work you have to set AC1 for pin 13  */
--of this damned GAL 16V8 to '1' manually after compiling it into a JEDEC */
--to make pin 13 an input.                                                */
--Othervise the pin 13 output of the GAL collides with the halt signal    */
--that is present on pin 13. This Lattice VHDL compiler keeps optimizing  */
--away any settings for pin 13 if it is unused in the design.             */
--Usually a GAL programmer offers the possibility to modify               */
--the fuse bits of the GAL before burning...                              */     
--                                                                        */
--*************************************************************************/
--                                                                        */
--Created by:                                                             */
--Christopher Lang, Jul. 2002, christopher.lang@plus.cablesurf.de         */
--                                                                        */
--*************************************************************************/


library ieee;
use ieee.std_logic_1164.all;

entity C025953PAL16L8_Entity is
	port (phi2, cas, halt, mhalt, cbe_pb4, vbe_pb5, ba14_pb2, ba15_pb3, mode: in std_logic;
              a: in std_logic_vector (15 downto 14);
              casmain, casbank: out std_logic;
    	      fa: out std_logic_vector (15 downto 14)
 	     );

attribute LOC: string;

attribute LOC of phi2: signal is "P19";
attribute LOC of a: signal is "P2;P1";
attribute LOC of ba14_pb2: signal is "P3";
attribute LOC of ba15_pb3: signal is "P4";
attribute LOC of cbe_pb4: signal is "P5";
attribute LOC of cas: signal is "P6";

attribute LOC of mhalt: signal is "P11";
attribute LOC of halt: signal is "P13";

attribute LOC of casbank: signal is "P14";
attribute LOC of casmain: signal is "P15";
attribute LOC of vbe_pb5: signal is "P18";
attribute LOC of mode: signal is "P12";

end;

--ssome stuff still from the Tango PLD version 
--ggroup bnksel_130[ba15_pb3, ba14_pb2];                    /* 64kb exp.  (130XE)
--ggroup bnksel_pb6[pb6, ba15_pb3, ba14_pb2];               /* 128kb exp. (PB6 only mode)
--ggroup bnksel_ger[pb7, pb6, ba15_pb3, ba14_pb2];          /* 256kb exp. ("German" or "Compy Shop" 320k)
--ggroup bnksel_usa[pb6, vbe_pb5, ba15_pb3, ba14_pb2];      /* 256kb exp. ("American 320k")
--ggroup bnksel_448[pb7, pb6, vbe_pb5, ba15_pb3, ba14_pb2]; /* 448kb exp. ("Chris's full 512k", 2 rows 256kbit chips



architecture C025953PAL16L8_Architecture of C025953PAL16L8_Entity is

signal casmain_through: std_logic;	-- lets make this low active
signal casbank_through: std_logic;	-- lets make this low active

constant high: std_logic := '1';
constant low:  std_logic := '0';

constant bank_page: std_logic_vector := "01";

constant mode_130xe: std_logic := '0';
constant mode_800xl: std_logic := '1';


begin


output_cas_signals: process (casmain_through, casbank_through, cas, phi2)

begin

	if casmain_through = low and phi2 = high then
		casmain <= cas;
	else
		casmain <= high;
	end if;

	if casbank_through = low and phi2 = high then
		casbank <= cas;
	else
		casbank <= high;
	end if;
end process output_cas_signals;



decode: process (cbe_pb4, vbe_pb5, ba14_pb2, ba15_pb3, a, mhalt, mode)
begin

  if a = bank_page then         -- access on $4000 to $7FFF occured

    case mode is

--ggroup bnksel_130[ba15_pb3, ba14_pb2];         /* 64kb exp.  (130XE)     */
    when mode_130xe =>          -- mode 130xe ******************************/

        if ( mhalt = high and cbe_pb4 = high )  -- CPU access on base RAM **/
          or ( mhalt = low and vbe_pb5 = high ) then -- Antic access on base RAM

          fa <= a;
	  casmain_through <= low; casbank_through <= high;
        else                                     -- access on extended RAM */
          fa <= ba15_pb3 & ba14_pb2;
	  casmain_through <= high; casbank_through <= low;
  	end if;



--ggroup bnksel_800xl
    when mode_800xl =>          -- mode 800xl only 64kb ********************/

        fa <= a;
	casmain_through <= low; casbank_through <= high;



--ggroup bnksel_130[ba15_pb3, ba14_pb2];         /* 64kb exp.  (130XE)     */   
    when others =>         -- mode 130xe ******************************/

        if ( mhalt = high and cbe_pb4 = high )  -- CPU access on base ram **/
          or ( mhalt = low and vbe_pb5 = high ) then -- Antic access on base RAM

          fa <= a;
          casmain_through <= low; casbank_through <= high;

        else                                     -- access on extended RAM */
          fa <= ba15_pb3 & ba14_pb2;
          casmain_through <= high; casbank_through <= low;
  	end if;
    end case;



  else
    fa <= a;
    casmain_through <= low; casbank_through <= high;
  end if;

end process decode;


end C025953PAL16L8_Architecture;