;Weenie Instructions ;These weenie instructions don't even alter memory, only registers and flags. ;They are CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX, TAY ;TSX, TXA, TXS, and TYA. They take two cycles. ;/////////////////////////////////////////////////////////////// ;// 3 Bars Background Effect Demo by Christian Bogey // ;// Friday, April 30, 2004 // ;/////////////////////////////////////////////////////////////// processor 6502 include "vcs.h" include "macro.h" SEG CODE ORG $F000 ; Start Adress Start ; Standard init code SEI ; Clear Interrups. The 6507 doesn't use interrupts but ; the program can run on a 7800 (6502) which use it. ; Prevent from interferences too : interrupt capabilities ; are included in the 6507 but the pins aren't linked. CLD LDX #$FF TXS Clear_Mem LDA #0 STA 0,X DEX BNE Clear_Mem ; Clear mem countdown from $FF to $01 ; >>>>>>>>> VBLANK Set to 0 Later ;some value ; ldx #0 c_s: lda mdata,x sta move_data,x inx cpx #16 bne c_s New_Frame ; Start of Vertical Sync LDA #2 STA VSYNC ; Turn VSYNC On ; Count 3 Scanlines STA WSYNC STA WSYNC STA WSYNC LDA #0 ; // 2 cycles STA VSYNC ; Turn VSYNC Off // 3 cycles ;>>>>>>>>>>>>> Start of Vertival Blank <<<<<<<<<<<<<<<<<<< ; Count 37 Scanlines LDA #43 ; // 2 cycles STA TIM64T ; // 4 cycles ;>>>>>>>>>>>>>>>> Free space for code starts here ;>>>>>>>>>>>>>>>> Free space for code ends here Wait_VBLANK_End LDA INTIM ; // 4 cycles BPL Wait_VBLANK_End ; // 3 cycles STA WSYNC ; // 3 cycles Total Amount = 21 cycles ; 2812-21 = 2791; 2791/64 = 43.60 LDA #0 STA VBLANK ; Enable TIA Output ;>>>>>>>>>>>>>>>> End of Vertival Blank <<<<<<<<<<<<<<<<<<< ;>>>>>>>>>>>>>>>> KERNAL starts here <<<<<<<<<<<<<<<<<<<<<< ; LDX #0 LDY #0 STA WSYNC ; 191 + 1 = 192 Scanlines ; NOP ; 2 Cycles ; JMP Loop1 ; + 3 Cycles // 5 Cycles are necessary for 2nd colour ; // bar alignment (Next frame build) Loop1 TYA ldx #0 cmp $8E bcc pt1 cmp $8F bcs pt1 ldx #$58 ; NTSC colors pt1 stx $FF ldx #0 cmp $86 bcc pt cmp $87 bcs pt ldx #$C6 ; NTSC colors pt txa eor $FF STA COLUBK ; 3 lda #0 STA WSYNC ; 4 INY;DEY ; 2 CPY #192 BNE Loop1 ; 3 ; overall 160 cycles ;2+3+24+3+20+3+2+4+2+3=66,68 horisontal blank LDX #0 STX COLUBK ;>>>>>>>>>>>>>>>> KERNAL ends here <<<<<<<<<<<<<<<<<<<<<<<< ;////////////// End Of Display //////////////////////////////////////// LDA #%00000010 ; Disable VIA Output STA VBLANK ; 30 Scanlines Overscan LDY #29 Loop2 STA WSYNC DEY BNE Loop2 STA WSYNC ; 29+1 = 30 ;////////////////////////////////////////////////// ; Build New Frame ldx #0 jsr calcmove sta $86 clc adc #$20 sta $87 ;and #$7F ; lda #$7F sta AUDF0 ;eor #$0F lda #2 sta AUDC0 lda #4 sta AUDV0 ldx #8 jsr calcmove sta $8E clc adc #$20 sta $8F JMP New_Frame move_data = $80 calcmove: lda move_data+1,X ; hl1+1 ; lsb,msb cmp move_data+5,X ;#$18+4 bcs zobra1 lda move_data+2,X ; de1 clc adc move_data+4,X ; #$20 sta move_data+2,X ; de1 bcc zobra0 inc move_data+3,X ;de1+1 zobra0 jmp zobra2 zobra1 lda move_data+2,X ;de1 sec sbc move_data+4,X ;#$20 sta move_data+2,X ;de1 lda move_data+3,X ;de1+1 sbc #$00 sta move_data+3,X ;de1+1 zobra2 lda move_data,X ;hl1 clc adc move_data+2,X ;de1 sta move_data,X ;hl1 lda move_data+1,X ;hl1+1 adc move_data+3,X ;de1+1 sta move_data+1,X ;hl1+1 ; value2 rts mdata: .byte 0,0 ;hl1 0 1 .byte 0,0 ;de1 2 3 .byte $26/2 ;bc 4 .byte $58 ; for cmp 5 .byte 0,0 ; 6 7 .byte 0,0 ;8 9 .byte 0,0 ;A B .byte $16 ;$16 ;C .byte $50 ; D .byte 0,0 ; E F parte: ORG $FFFA .word Start ; NMI - Not used by the 2600 but exists on a 7800 .word Start ; RESET .word Start ; IRQ - Not used by the 2600 but exists on a 7800 END